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- System modeling, device architecture and performance trade-off analysis and optimization
- Knowledgeable and experienced in the subject areas
Magnetic Storage, peripheral
Gigabit serial channel and transceivers
Optical read/write channel
OFDM(FFT/IFFT)
Digital signal processing
Analog front end interface
NAND Flash
EIDE/ATAPI/SATA |
Networking, router companion device
ARM AHB, AXI, APB, ARM9, ARM11
10 GE PCS/elastic buffers
Veterbi data decoder
DAC/ADC
Embedded Flash Memory
I2C PCI/PCIX/PCIE, DCP bus protocols
DDR |
- ASIC/Mixed-Signal/SoC design & verification
Verilog/VHDL coding, simulation
STA (static timing analysis)
Functional and ATPG vector generation |
Design review, audit and verification
Design for test (scan, BSD, BIST)
Mixed-Signal design and verification |
Design and integration of IP (digital & analog)
Low power sysnthesis and optimization (Multi-Vt, clock gating and sleep mode)
Block level and complex multi-million gates system level design verification |
- ASIC/Mixed-Signal/SoC GDSII creation
Floor plan, physical synthesis, place & route
Stream-lined SP&R with DFT and Power Synthesis to tape out
DRC/LVS/Antenna and GDSII touch-up |
- FPGA prototyping conversion
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